Most conversations about artificial intelligence happen at the software level: model releases, benchmark scores and demos that go viral overnight.
The intelligence people talk about does not float in the cloud. It runs on physical silicon, fabricated to tolerances measured in atoms. The gap between what a model promises and what hardware can actually deliver is where much of the real engineering happens.
Shashikiran Konnur Sampathkumar, an IP logic design engineer at Intel and a senior member of IEEE, puts that physical reality at the center of his new book, The Silicon Pulse: How the Senior Leaders in Semiconductors, AI, and the New Architecture of Power Are Reshaping the Industry.
His argument is straightforward. AI is not abstract. It is physical, and the future of the field will be decided as much in the fab as in the lab.
Sampathkumar writes from inside that stack. For more than a decade, he has worked across the semiconductor product lifecycle, from IP design to high-volume manufacturing, collaborating with foundries including TSMC and Samsung across advanced process nodes and leading technology transfers across three continents.
A practitioner’s case for the physical layer of AI
Technology coverage often treats hardware as a solved background detail, a commodity that scales while the most interesting work happens in software.
Sampathkumar pushes back on that view. Every model release, he argues, rests on a chain of physical decisions, from how a transistor is laid out to how heat leaves a data center. A weakness anywhere in that chain can limit what the software on top can do.
Compute is not an unlimited resource waiting to be summoned. It is manufactured one wafer at a time, with yields that shape cost, supply and timelines. The book treats semiconductors as the strategic foundation of the AI era rather than its plumbing.
“People talk about AI as if it lives in the cloud,” Sampathkumar said. “It lives in a fab. Every capability you see in a model was paid for in physics, in yield, and in years of process engineering.”
From the model layer to the silicon beneath it
The book moves deliberately down the stack.
It starts where many readers are most comfortable, with systems and models, then moves into architecture, register-transfer-level design and the transistor physics that determine whether a chip works at 3 nanometers at all.
The purpose is to show how tightly each layer constrains the others.
Sampathkumar presents the industry as a set of trade-offs rather than a simple march of progress. A gain in performance often comes with a cost in power, area or reliability. The job is deciding which constraint can be relaxed and which cannot.
“Nothing in this field is free,” Sampathkumar said. “Every improvement is a negotiation between speed, power, area, and cost. The skill is knowing which one you can afford to give up.”
Lessons from the fab floor
The book’s authority rests on work Sampathkumar has done across the semiconductor lifecycle.
Early in his career at Intel, he helped pioneer the company’s first die sort methodology across the 14-nanometer and 10-nanometer nodes, a way of identifying defective chips at the wafer level before they reach more expensive packaging stages.
The approach improved throughput efficiency and wafer yield while helping establish the Known Good Die standard, the practice of certifying individual chips before assembly.
His more recent work operates closer to the leading edge of process technology.
Sampathkumar leads RTL design for Intel’s first ARM-based fuse controller IP built for external foundries, a component that has to be correct the first time because a faulty fuse can permanently disable a chip. Through architecture and synthesis optimization, the design reduced area and power while meeting automotive-grade reliability standards for high-volume production.
Designing for the edge of physics
One of the book’s recurring themes is how unforgiving advanced nodes have become.
At 3 nanometers, tolerances shrink to the point where small physical variation can ripple into a major yield problem, and even a modest change in yield can shift the economics of a product.
Sampathkumar uses that sensitivity to explain why much of chip design is really risk management.
Verification of a complex IP block can involve hundreds of formal assertions and thousands of test cases because the cost of a defect that escapes into production is enormous. In safety-critical parts, the consequences can extend beyond cost.
The book treats reliability not as a quality checkbox but as a central design constraint at the leading edge.
“At these dimensions, there is no room to be approximately right,” Sampathkumar said. “A part either holds up across millions of units in the field, or it does not, and you find out the expensive way.”
Beyond the book
Sampathkumar’s contributions extend beyond the manuscript.
A senior member of IEEE and a panel reviewer for the organization, he also serves on the editorial team of the International Journal of Emerging Research in Engineering and Technology and has judged technical hackathons and industry awards programs.
His career has carried him across design, validation and manufacturing on three continents, giving the book a practical range that connects a line of RTL to a factory floor without losing the thread.
The road ahead
The Silicon Pulse arrives as compute has become a strategic question.
Governments now treat chip fabrication as a matter of national capability. The energy and water used by large data centers have become public concerns. Hardware security matters more as compute becomes a strategic asset.
Sampathkumar’s view is that where to build, what to fund and how much environmental cost to accept for intelligence at scale are choices, not inevitabilities.
“The pulse is still speeding up,” Sampathkumar said. “What matters now is not whether we can build more compute, but what we choose to optimize for, and what we decide we are not willing to trade away.”